Various isolation structures are presently used for fabricating semiconductor devices. These isolation structures are used in order to isolate adjacent electronic devices (such as transistors) which are formed in fabricating certain semiconductor circuits.
Typically, isolation structures are created using the well-known local Oxidation of Silicon (LOCOS) isolation technique. The disadvantage to this process is that the silicon dioxide (isolator) is grown in an isotropic manner which consumes surface area on the semiconductor circuit and causes the adjacent electronic devices that are being isolated to be a fixed minimum distance apart. This limits the density of the electronic devices on each microchip.
Another technique used to create isolation structures is by using a trench. This method is known as Shallow Trench Isolation (STI). In the STI process, a pad-oxide (SiO.sub.2) layer is grown on the semiconductor substrate after which a silicon nitride (Si.sub.3 N.sub.4) layer is then deposited on the pad-oxide layer. Using well known methods the pad oxide/silicon nitride is patterned and etched to the determined widths of the isolation structures. Next, the semiconductor substrate is etched to form trenches and the surface is deposited with silicon dioxide to fill the trenches above the top of the silicon nitride surface.
Again using well known methods, the semiconductor device is reverse patterned and etched before the surface is planarized using CMP to remove the silicon dioxide from covering the nitride. Reverse patterned meaning the inverse of the trench pattern is used to etch the silicon oxide over the silicon nitride. Finally, the nitride is removed from the surface and the electronic devices may be built on the semiconductor substrate surface.
Three distinct disadvantages exist using this well known method. The most dominant disadvantage is cost. The extra mask adds a resist coat, mask expose and resist develop steps. Also added are an extra etch step and post photo clean step.
Another disadvantage to this method is that the slurry used to polish at CMP has a selectivity of &lt;5:1, silicon dioxide polish rate to silicon nitride polish rate. The reverse etch process is required to eliminate substrate damage. Damage occurs in the isolated regions because the oxide in an area with a large percentage of trenches polishes at a much higher rate than the oxide over the nitride in a dense area of moats. Therefore, reverse etch is used to evenly distribute the density of the amount of oxide to be polished. The reverse etch processes require a pattern and an etch, thereby increasing the expense of wafer fabrication. Current CMP processes in STI applications without patterned etch back using conventional slurries would cause damage to the substrate in isolated regions while possibly not removing the silicon dioxide from the large or dense regions of nitride, making it unsuitable for production use.
The third known disadvantage is that the silicon dioxide formed after the reverse pattern and etch is able to break off and causes scratching during the CMP process.
Machines for fabricating semiconductor circuits are known in the art. CMP polishing of the wafers is used to form a planar surface at different levels of fabrication or to polish back to a surface after filling trenches or interconnects. In general, the polishing process is accomplished by bringing a wafer mounted on a rotating carrier into contact with a rotating polishing pad upon which is sprayed a slurry of insoluble abrasive particles suspended in an acidic or basic solution. CMP is the combination of mechanical and chemical abrasion; material is removed from the wafer due to both the mechanical buffing and the action of the acid or base.
The CMP process is known to provide excellent local planarity. Planarity is affected by feature height, size, layout, and density of the semiconductor device as well as by the polishing conditions such as mechanical polishing parameters, pad, and slurry.
Various methods have been attempted to remove the non-value added reverse etch process. Boyd and Ellul (J. M. Boyd, et al., Electochem. Soc. Proc., Vol. 95-5, 1996, p. 290) reported the use of a thin nitride overcoat deposited on top of the gap filled oxide to reduce dishing. The nitride overcoat provides protection to the underlying oxide in low lying regions while the high level oxide is being polished at a much faster rate due to the oxide:nitride selectivity of 4:1.